裝配圖單片機(jī)實(shí)現(xiàn)的步進(jìn)電機(jī)控制系統(tǒng)（開(kāi)題報(bào)告+論文+文獻(xiàn)綜述+外文翻譯+DWG圖紙）

裝配圖單片機(jī)實(shí)現(xiàn)的步進(jìn)電機(jī)控制系統(tǒng)（開(kāi)題報(bào)告+論文+文獻(xiàn)綜述+外文翻譯+DWG圖紙）,裝配,單片機(jī),實(shí)現(xiàn),步進(jìn),電機(jī),機(jī)電,控制系統(tǒng),開(kāi)題,報(bào)告,講演,呈文,論文,文獻(xiàn),綜述,外文,翻譯,dwg,圖紙 浙江工業(yè)大學(xué)浙西分校信電系系畢業(yè)論文(中英文資料) Modeling micro-controller peripherals for high-level co-simulation and synthesis Mapping a behavior on an embedded system involves hardware-software partitioning and assignment of software and hardware tasks to different components. In particular, software tasks in embedded controllers are mostly assigned to a micro-controller. However, some micro-controller peripherals are implemented with partly programmable components that can be regarded as very simple co-processors with limited instruction sets and capabilities. Embedded system designers are used to mapping some simple software tasks onto these simple co-processors, obtaining overall performances that can be orders of magnitude superior to the ones obtained mapping all software tasks to the micro-controller itself. In this paper, we propose a methodology to specify, simulate, and partition tasks that can be implemented on programmable micro-controller peripherals such as Timing Processing Units P U S ) . Following our general philosophy, we let the designer propose a partition, and we provide an environment 0 to efficiently simulate and evaluate a particular implementation choice 0 to automate downstream synthesis for software, hardware, as well as peripheral programming routines. 1 Implementation and Case Study We have implemented such a library for the 68hcll family of micro-controllers from Motorola . It includes: 0 The timer unit, implementing input capture and output compare functions, that measure time between input and 0 The ALII convert output events using a 16 bit free running counter. 0 The PWM generators present on a specific family member targeted for automotive applications. Each function of the timer unit and of the PWM generator is described both at the behavioral level, using the simulator timing functions to implement time, and at the Register Transfer level, using a cycle-accurate model of the hardware. The latter is also used for hardware and software synthesis, if the peripheral is not used. C routines are used to interface to the peripheral. The precision of the RTL model can be scaled, by dividing the clock. A single simulation parameter controls this scaling without affecting the overall behavior (apart from the loss of precision). We have specified the functionality of a complete dashboard controller, that uses the 68hcl1 peripherals. Note, with the standard co-design methods, using only fully programmable processors or hardware, all the tasks implemented by the peripherals could be implemented only as software tasks, thus yielding a less performing solution, or as hardware tasks, thus yielding a higher cost and less flexible solution. Hence the method presented here is required in order to obtain a solution quality comparable with manual design. The speed of the behavioral simulation was about 260,000 clock cycles per second. The speed of the RTL simulation ranged almost linearly from 2,000 clock cycles per second to 50,000 clock cycles depending on the clock scaling factor, from 1 to 32. The experiments were performed on a 60MHz ULTRAsparc. At synthesis time, the appropriate U 0 drivers are extracted from the library and customized by the co-design tools. We also synthesized a hardware implementation for the PWM generators of the dashboard controller, because they are not available on all members of the 68hcll family. We analyzed the cost trade-offs of using some small ASIC to implement that function. A hardware implementation, using XILINX FPGAs for rapid prototyping purposes required 374 CLBs (with 203 flip-flops) and 60 U 0 pads, that would fit on a XILINX 4010 chip. 2 Conclusion The proposed solution for high-level specification of micro-controller peripherals retains most of the advantages and flexibility of hardware software co-design (uniform modeling, fast co-simulation, formal verification, flexibility in target implementation,. The limit is that the designer has to decide on whether or not a function is implementable using a particular peripheral, and sometimes such a decision must be made about peripherals that may be only slightly different between different micro-controllers. Further research is still needed to develop mapping techniques from an unbiased specification to partially programmable devices. 模擬單片機(jī)外設(shè)的高級(jí)共仿真和綜合 映射在一個(gè)嵌入系統(tǒng)上的行為包括硬件-軟件區(qū)分和對(duì)于不同成分上硬件和軟件的任務(wù)。特別的,在嵌入控制上的軟件任務(wù)由單片機(jī)執(zhí)行。但是,一些單片機(jī)外圍設(shè)備一起實(shí)現(xiàn)部分可設(shè)計(jì)的成分,這些成分被當(dāng)作限制性的指令組合和能力的非常簡(jiǎn)單的共處理器。嵌入系統(tǒng)設(shè)計(jì)者習(xí)慣于把一些簡(jiǎn)單的軟件工作映射到這些簡(jiǎn)單的共處理器,以獲得把大規(guī)模指令轉(zhuǎn)向獲得映射所有軟件任務(wù)的單片機(jī)本身。本文,我們打算一種方法去敘述,仿真,和區(qū)分那些可能是被用于可設(shè)計(jì)的單片機(jī)外圍設(shè)備,比如時(shí)間處理單元(TPUs)。通過(guò)我們的一般原理,我們讓設(shè)計(jì)者計(jì)劃分割,且我們提供一個(gè)環(huán)境去有效仿真和評(píng)估一個(gè)特殊執(zhí)行選擇。為軟件,硬件和外圍設(shè)備規(guī)劃常式自動(dòng)化下游的綜合。 1、落實(shí)和個(gè)案研究 我們已經(jīng)實(shí)現(xiàn)了來(lái)自摩托羅拉的單片機(jī)68hcll系列。它包括:定時(shí)單元,實(shí)現(xiàn)輸入攝入輸出比較功能,使用16位自由運(yùn)行計(jì)算器的輸入和輸出兩者間的測(cè)試時(shí)間。 A/D轉(zhuǎn)換器 PWM 產(chǎn)生器在一個(gè)特定的系列成員上為汽車(chē)的申請(qǐng)對(duì)準(zhǔn)。 我們已經(jīng)敘述完全的儀表板控制器的功能性,這些控制器使用 68 hcl1 外圍設(shè)備。注意共設(shè)計(jì)方法的標(biāo)準(zhǔn), 使用只有完全可設(shè)計(jì)的處理器或硬件,所有的被外設(shè)實(shí)現(xiàn)的工作能僅僅如軟件工作那樣實(shí)現(xiàn),如此產(chǎn)生一個(gè)更高的成本和更少靈活的方法。因此,在這里呈現(xiàn)的方法被要求為了獲得一個(gè)解決特性相比較手動(dòng)設(shè)計(jì)。 行為模擬速度大約是260000時(shí)鐘循環(huán)每秒。RTL模擬速度范圍從2000時(shí)鐘循環(huán)每秒到5000時(shí)鐘循環(huán)每秒線性變化,依靠時(shí)鐘計(jì)數(shù)因素，從1到32。試驗(yàn)在60MHZ的ULTRAsparc上被運(yùn)行。 綜合時(shí)間,適當(dāng)?shù)腎/O驅(qū)動(dòng)從圖書(shū)館和有共設(shè)計(jì)工具的客戶(hù)上被修改。我們也為儀表板控制器的 PWM 產(chǎn)生器綜合硬件實(shí)現(xiàn),因?yàn)樗麄冊(cè)?8hcll單片機(jī)系列所有成員不是適當(dāng)?shù)?。我們分析了使用一些小ASIC的稱(chēng)本交換去實(shí)現(xiàn)這個(gè)功能。一個(gè)硬件實(shí)現(xiàn),使用XILINX FPGAs作為快速設(shè)計(jì)原型的目的要求374CLBs和60I/O Pads,這些將在XILINX4010芯片上使用。 2、結(jié)論 單片機(jī)外設(shè)的高級(jí)外設(shè)的提議解決方法保留了共設(shè)計(jì)硬件/軟件的大部分優(yōu)點(diǎn)和靈活性。局限是設(shè)計(jì)者不得不考慮一個(gè)功能是否要用一個(gè)特殊外設(shè)去實(shí)現(xiàn),且有時(shí)如此的決定必須作出有關(guān)不同單片機(jī)外設(shè)之間的微小差別。更進(jìn)一步的研究仍然需要去發(fā)展映射技術(shù)從無(wú)偏見(jiàn)外設(shè)到局部可編程的裝置。