多功能工業(yè)控制平臺(tái)
多功能工業(yè)控制平臺(tái),多功能,工業(yè),控制,節(jié)制,平臺(tái)
級(jí)學(xué)生畢業(yè)設(shè)計(jì)（論文）中期報(bào)告
系別
班級(jí)
學(xué)生
姓名
指導(dǎo)
教師
課題名稱：多功能工業(yè)控制平臺(tái)
簡述開題以來所做的具體工作、取得的進(jìn)展及下一步主要工作：
所做的工作：
1. 在圖書館和網(wǎng)絡(luò)上查找相關(guān)資料，了解MSP430F149單片機(jī)的功能和工程開發(fā)的應(yīng)用，為深入研究做好準(zhǔn)備。
2. 查找各器件的管腳圖及其原理，列元件清單，購買器件。
3. 根據(jù)之前的準(zhǔn)備進(jìn)行電路的焊接工作，從元器件的特性，電路的外觀上合理的布局，完成硬件電路焊接。
4.對(duì)電路進(jìn)行調(diào)試。
取得的進(jìn)展：
各模塊電路已基本實(shí)現(xiàn)，獲得的指標(biāo)和設(shè)想差距不大。
下一步的主要工作：
1. 解決調(diào)試中出現(xiàn)的問題，并且分析其原因。
2. 記錄調(diào)試數(shù)據(jù)，整理資料，準(zhǔn)備寫論文。
3. 總結(jié)之前所作的工作，為畢業(yè)答辯做好充分的準(zhǔn)備。
學(xué)生簽字：
年 月 日
指導(dǎo)教師的建議與要求：
設(shè)計(jì)思路清晰，進(jìn)度安排合理，同時(shí)希望在以后的制作過程中要抓緊時(shí)間
完成后期的工作。
指導(dǎo)教師簽字：
年 月 日
英文資料及中文翻譯
1．英文資料
The Design of a Rapid Prototype Platform for ARM Based Embedded System
Hardware prototype is a vital step in the embedded system design. In this paper, we discuss our design of a fast prototyping platform for ARM based embedded systems, providing a low-cost solution to meet the request of flexibility and testability in embedded system prototype development. It also encourages concurrent development of different parts of system hardware as well as module reusing.
Though the fast prototyping platform is designed for ARM based embedded system, our idea is general and can be applied to embedded system of other types.
I.INTRODUCTION
Embedded systems are found everywhere, including in cellular telephones, pagers, VCRs, camcorders, thermostats, curbside rental-car check-in devices, automated supermarket stockers, computerized inventory control devices, digital thermometers, telephone answering machines, printers, portable video games, TV set-top boxes -- the list goes on. Demand for embedded system is large, and is growing rapidly.
In order to deliver correct-the-first-time products with complex system requirements and time-to-market pressure, design verification is vital in the embedded system design process. A possible choice for verification is to simulate the system being designed. If a high-level model for the system is used, simulation is fast but may not be accurate enough, with a low-level model too much time may be required to achieve the desired level of confidence in the quality of the evaluation. Since debugging of real systems has to take into account the behavior of the target system as well as its environment, runtime information is extremely important. Therefore, static analysis with simulation methods is too slow and not sufficient. And simulation cannot reveal deep issues in real physical system.
A hardware prototype is a faithful representation of the final design, guarantying its real-time behavior. And it is also the basic tool to find deep bugs in the hardware. For these reasons, it has become a crucial step in the whole design flow. Traditionally, a prototype is designed similarly to the target system with all the connections fixed on the PCB (printed circuit boards).
As embedded systems are getting more complex, the needs for thorough testing become increasingly important. Advances in surface-mount packaging and multiple-layer PCB fabrication have resulted in smaller boards and more compact layout, making traditional test methods, e.g., external test probes and "bed-of-nails" test fixtures, harder to implement. As a result, acquiring signals on boards, which is beneficial to hardware testing and software development, becomes infeasible, and tracking bugs in prototype becomes increasingly difficult. Thus the prototype design has to take account of testability. However, simply adding some test points is not enough. If errors on the prototype are detected, such as misconnections of signals, it could be impossible to correct them on the multiple-layer PCB board with all the components mounted. All these would lead to another round of prototype fabrication, making development time extend and cost increase.
Besides testability, it is important to maintain high flexibility during development of the prototype as design specification changes are common. Nowadays complex systems are often not built from scratch but are assembled by reusing previously designed modules or off-the-shelf components such as processors, memories or peripheral circuitry in order to cope with more aggressive time-to-market constraints. Following the top-down design methodology, lots of effort in the design process is spent on decomposing the customers, requirements into proper functional modules and interfacing them to compose the target system.
Some previous research works have suggested that FPLDs (field programmable logic device) could be added to the final design to provide flexibility as FPLDs can offer programmable interconnections among their pins and many more advantages. However, extra devices may increase production cost and power dissipation, weakening the market competition power of the target system. To address these problems, there are also suggestions that FPLDs could be used in hardware prototype as an intermediate approach [1]-[3], whereas this would still bring much additional work to the prototype design. Moreover, modules on the prototype cannot be reused directly. In industry, there have been companies that provide commercial solutions based on FPLDs for rapid prototyping [4]. Their products are aimed at SOC (system on a chip) functional verification instead of embedded system design and development.
In this paper, we discuss our design of a Rapid Prototyping Platform for ARM based Embedded System, providing a low cost solution to meet the request of flexibility and testability in embedded system prototype development. It also encourages concurrent development of different parts of system hardware as well as module reusing. The rest of the paper is organized as follows. In section 2, we discuss the details of our rapid prototyping platform. Section 3 shows the experimental results, followed by an overall conclusion in section 4.
II. THE DESIGN OF A RAPID PROTOTYPING PLATFORM
A. Overview
ARM based embedded processors are wildly used in embedded systems due to their low-cost, low-power consumption and high performance. An ARM based embedded processor is a highly integrated SOC including an ARM core with a variety of different system peripherals[5]. Many arm based embedded processors, e.g.[6]-[8], adopt a similar architecture as the one shown in Fig. 1.
The integrated memory controller provides an external memory bus interface supporting various memory chips and various operation modes (synchronous, asynchronous, burst modes). It is also possible to connect bus-extended peripheral chips to the memory bus. The on-chip peripherals may include interrupt controller, OS timer, UART, I2C, PWM, AC97, and etc. Some of these peripherals signals are multiplexed with general-purpose digital I/O pins to provide flexibility to user while other on-chip peripherals, e.g. USB host/client, may have dedicated peripheral signal pins. By connecting or extending these pins, user may use these onchip peripherals. When the on-chip peripherals cannot fulfill the requirement of the target system, extra peripheral chips have to be extended.
The architecture of an ARM based embedded system is shown in Fig. 2. The whole system is composed of embedded processor, memory devices, and peripheral devices. To enable rapid prototyping, the platform should be capable of quickly assembling parts of the system into a whole through flexible interconnection. Our basic idea is to insert a reconfigurable interconnection module composed by FPLD into the system to provide adjustable connections between signals, and to provide testability as well. To determine where to place this module, we first analyze the architecture of the system.
The embedded system shown in Fig. 2 can be divided into two parts. One is the minimal system composed of the embedded processor and memory devices. The other is made up of peripheral devices extended directly from on-chip peripheral interfaces of the embedded processor, and specific peripheral chips and circuits extended by the bus.
The minimal system is the core of the embedded system, determining its processing capacity. The embedded processors are now routinely available at clock speeds of up to 400MHz, and will climb still further. The speed of the bus connecting the processor and the memory chips is exceeding 100MHz. As pin-to-pin propagation delay of a FPLD is in the magnitude of a few nanoseconds, inserting such a device will greatly impair the system performance.
The peripherals enable the embedded system to communicate and interactive with the circumstance in the real world. In general, peripheral circuits are highly modularized and independent to each other, and there are hardly needs for flexible connections between them.
Here we apply a reconfigurable interconnection module to substitute the connections between microcomputer and the peripherals, which enables flexible adjusting of connections to facilitate interfacing extended peripheral circuits and modules. As the speed of the data communication between the peripherals and the processor is much slower than that in the minimal system, the FPLD solution is feasible.
Following this idea, we design the Rapid Prototyping Platform as shown in Fig. 3. We define the interface ICB between the platform and the embedded processor core boar that holds the minimal system of the target embedded system. The interface IPB between the platform and peripheral boards that hold extended peripheral circuits and modules is also defined. These enable us to develop different parts of the target embedded system concurrently and to compose them into a prototype rapidly, and encourage module reusing as well. The two interfaces are connected by a reconfigurable interconnect module. There are also some commonly used peripheral modules, e.g. RS232 transceiver module, bus extended Ethernet module, AC97 codec, PCMCIA/CompactFlash Card slot, and etc, on the platform which can be interfaced through the reconfigurable interconnect module to expedite the embedded system development.
B. Reconfigurable Interconnect Module
With the facility of state-of-arts FPLDs, we design a reconfigure interconnection module to interconnect, monitor and test the bus and I/O signals between the minimal system and peripherals.
As the bus accessing obeys specific protocol and has control signals to identify the data direction, the interconnection of the bus can be easily realized by designing a corresponding bus transceiver into the FPLD, whereas the interconnection of the I/Os is more complex. As I/Os are multiplexed with on-chip peripherals signals, there may be I/Os with bi-direction signals, e.g. the signals for on-chip I2C[9] interface, or signals for on-chip MMC (Multi Media Card[10]) interface. The data direction on these pins may alter without an external indication, making it difficult to connect them via a FPLD. One possible solution is to design a complex state machine according to corresponding accessing protocol to control the data transfer direction. In our design we assign specific locations on the ICB and IPB interfaces to these bi-direction signals and use some jumpers to directly connect these signals when needed. The problem is circumvented at the expense of losing some flexibility.
The use of FPLD to build the interconnection module not only offers low cost and simple architecture for fast prototyping, but also provides many more advantages. First, interconnections can be changed dynamically through internal logic modification and pin re-assignment to the FPLD. Second, as FPLD is connected with most pins from the embedded processor, it is feasible to detect interconnection problems due to design or physical fabricate fault in the minimal system with BST (Boundary-Scan Test, IEEE Standard 1149.1 specification). Third, it is possible to route the FPLD internal signals and data to the FPLD’s I/O pins for quick and easy access without affecting the whole system design and performance. It is even possible to implement an embedded logical analyzer into the FPLD to smooth the progress of the hardware verification and software development.
C. Power Supply
Power dissipation has a great impact on system cost and reliability. It is an increasingly important problem in embedded systems designs not only for the portable
electronics industry but in other areas including consumer electronics, industry control, communications, etc. In order to facilitate the design of power supply for the target embedded system, power supply issues have also been considered in the design of the platform.
First, the power supplies to the devices on the platform are separated from those to the core board and peripheral expand boards, which makes it more realistic to measure and verify the power dissipation on the platform for the target embedded system. Second, the power supplies for the core board and peripheral expand boards are built on a separate board and connected to the platform through a slot. As a result, it provides flexibility for power system design while speeding up the whole design process.
To meet the demand for higher system speed and lower power consumption in data communications and processing, embedded processor vendors use increasingly advanced processing technologies requiring lower core operating voltages, and keep the interface voltage compatible with most low voltage semiconductor devices on market. Consequently, almost every embedded processor requires more than one power supply, such as power supply for internal logic, for PLLs and oscillators, for memory bus interface, and for other I/Os. Further, different embedded processors may have different requirements on power supply, such as different power supply voltage, power-up sequence, and different strategies to adjust the core voltage in different CPU run mode for minimizing power dissipation.
A survey of some widely used ARM based embedded processor suggests that most of them need no more than 3 groups of separated power supply, as shown in Table 1. As the peripherals may require different supply voltages for special purpose, such as +5V for powering the USB ports, we divide the power supply from the power supply slot into 4 separated channels, which is connected to both the core board slot and the peripheral board slot. Each channel of power supplies has a “power good” signal to indicate power output status of the channel, and a shutdown signal to shut the power supply of the channel down. And these signals are directly connected to the core board slot to accommodate the embedded processor’s requirement of power-up sequence. In order to enable dynamic voltage adjusting, some control signals are routed to the power supply board by the reconfigurable interconnect module.
III. EXPERIMENTAL RESULTS
As the Rapid Prototyping Platform is still under development, we present an example applied with the same considerations in the Rapid Prototyping Platform. It is an embedded system prototype based on Intel XScale PXA255, which is an ARM based embedded processor. The diagram of the prototype is illustrated in Fig. 5(a). The photo is shown in Fig. 5(b), where a Bluetooth module is connected to the prototype USB port and a CF LAN card is inserted.
The FPGA (an Altera Cyclone EP1C6F256) here offers the same function as the reconfigurable interconnection module shown in Fig. 3. Most of the peripheral devices are expanded to the system through the FPGA, and more peripherals can be easily interfaced when needed. As both of the FPGA and PXA255 support the BST, we can detect faults, e.g. short-circuit and open-circuit faults, on the connections between the two devices by chaining their JTAG ports and performing BST. Here, we use an open source software package [11] to perform the BST.
The FPGA internal signals can be routed to the debugging LED matrix for easy access, which is helpful in some simple testing and debugging. We also insert an embedded logical analyzer, the SignalTap II embedded logic analyzer [12] provided in Altera’s Quartus II software, into the FPGA for handling more complicated situations. With the help of the logical analyzer, we are able to capture and monitor data passing through over a period of time, which expedites the debugging process for the prototype system. Fig. 6 shows the captured data communication between the embedded processor and the USB host module during the initialization process of the Philips ISP1161 USB host chip[13]. It can be seen clearly from the figure that the embedded processor writes the command code of 0027H to address 01H (the ISP1161’s host controller command port) to access the HcChipID register, and reads 6120H (the chip’s ID) from address 00H (the ISP1161’s host controller data port).
The power supply module of the prototype system is held on a separate board connected to the system via a socket. We designed two power supply modules for the prototype system (shown in Fig. 7). One is a large module providing fixed output composed with simple but low-efficiency linear regulator (the upside one in the Fig. 7), the other is a compact module, capable of dynamic voltage adjusting, made up of complex high-efficiency switch regulator(the downside one in the Fig. 7). The former module is first used to accommodate the basic power supply requirements during hardware test and relative software development. During the process, the later is developed and refined, and replaced the former one finally. The separation of power supply module from prototype allows refinement of the power supply module without affecting development of other parts of the system.
In this paper, we discuss the design of a fast prototyping platform for ARM based embedded systems to accommodate the requirements of flexibility and testability in the prototyping phase of an embedded system development.
With the aid of the platform, modules of the target embedded system can be developed simultaneously, and previous modules can be applied to future designs. As a result, develop process is greatly accelerated.
Though the fast prototyping platform is designed for ARM based embedded system, our idea is general and can be applied to embedded system of other types.
2．中文資料
基于ARM的嵌入式系統(tǒng)的速成樣機(jī)平臺(tái)設(shè)計(jì)
在嵌入式系統(tǒng)的設(shè)計(jì)中，硬件模型的設(shè)計(jì)是非常重要的。在這篇論文中，我們將討論一種我們自行設(shè)計(jì)的快速模型平臺(tái)，這是基于ARM的嵌入式系統(tǒng)的。這是一種低成本的設(shè)計(jì)方法，并且符合在嵌入式系統(tǒng)模型發(fā)展上對(duì)于靈活性和易測(cè)試性的要求。我們提供的方法同樣支持系統(tǒng)硬件模塊各個(gè)部分的更新和重利用。
雖然快速模型平臺(tái)是為基于ARM的嵌入式系統(tǒng)設(shè)計(jì)的，但是我們的方法是普遍適用的而且可以被廣泛應(yīng)用于其它各種類型的嵌入式系統(tǒng)。
1．介紹
嵌入式系統(tǒng)的應(yīng)用非常廣泛，例如在手機(jī)、尋呼機(jī)、錄像機(jī)、可攜式攝像機(jī)、自動(dòng)調(diào)溫器、路邊租用汽車的登記設(shè)備、自動(dòng)售貨機(jī)、用計(jì)算機(jī)處理存貨清單的控制設(shè)備、數(shù)字體溫計(jì)、電話應(yīng)答機(jī)、打印機(jī)、便攜式視頻游戲、機(jī)頂盒——還可列出很多。對(duì)于嵌入式系統(tǒng)的需求是巨大的，同樣它的發(fā)展也是很快的。
為了生產(chǎn)出滿足復(fù)雜系統(tǒng)要求而且適應(yīng)市場(chǎng)的正確的、第一手產(chǎn)品，設(shè)計(jì)的確認(rèn)工作在整個(gè)設(shè)計(jì)過程中是非常關(guān)鍵的。對(duì)于確認(rèn)，一個(gè)可能的選擇是模仿已經(jīng)設(shè)計(jì)出的系統(tǒng)。但是如果系統(tǒng)要求一個(gè)高水平的模型，，那么模仿雖然快可就不可能非常準(zhǔn)確，因?yàn)榈退降哪Ｐ椭荒軡M足一般質(zhì)量評(píng)估的要求。一旦實(shí)時(shí)系統(tǒng)的調(diào)試要考慮進(jìn)去，目標(biāo)系統(tǒng)、還有它的環(huán)境、及其運(yùn)行信息就顯得特別重要。因此，用模仿的方法來做的靜態(tài)分析機(jī)會(huì)讓人感覺效率太低。而且模仿不能揭示在實(shí)時(shí)物理系統(tǒng)方面更深層次的問題。
一個(gè)硬件樣機(jī)是最終設(shè)計(jì)的可考代表，它保證了實(shí)時(shí)行為。同時(shí)它也是發(fā)現(xiàn)硬件深層次問題的基礎(chǔ)工具。正是由于這些原因，硬件樣機(jī)設(shè)計(jì)成為整個(gè)設(shè)計(jì)流程中非常重要的一步。傳統(tǒng)上，樣機(jī)設(shè)計(jì)的都與它的目標(biāo)系統(tǒng)的PCB版很相似。
隨著嵌入式系統(tǒng)變得越來越復(fù)雜，對(duì)于系統(tǒng)的測(cè)試就顯得越來越重要。表面設(shè)置組件和多層PCB板的發(fā)展，導(dǎo)致了更小的板子和更緊湊的版面設(shè)計(jì)。這就使得傳統(tǒng)的測(cè)試方法，例如：外部探測(cè)器和“釘板”測(cè)試裝置，很難實(shí)現(xiàn)。結(jié)果，從板子上獲得對(duì)硬件測(cè)試和軟件開發(fā)有用的信號(hào)變得不可行，而且使在樣機(jī)上查找錯(cuò)誤變得越來越難。因此，樣機(jī)的設(shè)計(jì)必須考慮可測(cè)試性。然而，簡單的加一些測(cè)試點(diǎn)是不夠的。如果樣機(jī)上的錯(cuò)誤被檢測(cè)出來，比如信號(hào)的錯(cuò)誤連接，那么那是不可能在多層且與各種設(shè)置都緊密相關(guān)的PCB板上糾正的。因?yàn)檫@些都會(huì)影響到樣機(jī)上的其它設(shè)置，增加項(xiàng)目開發(fā)的時(shí)間同時(shí)會(huì)提高成本。
除了可測(cè)試性，保持樣機(jī)在開發(fā)過程中的高度靈活性也是非常重要的，因?yàn)樵O(shè)計(jì)規(guī)格是會(huì)經(jīng)常改動(dòng)的。目前復(fù)雜系統(tǒng)常常不是拼湊在一起的，而是會(huì)利用先前已經(jīng)設(shè)計(jì)的一些模塊，像是：處理器、存儲(chǔ)器、或是外圍電路。這樣做是為了應(yīng)付越來越激烈的市場(chǎng)競爭的壓力。按照這些嚴(yán)密的方法論，我們就會(huì)明白設(shè)計(jì)時(shí)的大部分精力放在：將用戶的需求拆分成合適的功能模塊和再組成目標(biāo)系統(tǒng)上。
很多以前的研究結(jié)論建議：將FPLDs添加到最終的設(shè)計(jì)中以增加系統(tǒng)的靈活性，因?yàn)镕PLDs可以在它們的管腳間提供可編程的連接而且還可以帶來其他一些好處。然而，外加設(shè)備可能會(huì)增加產(chǎn)品的成本和電源的負(fù)擔(dān)，減弱目標(biāo)系統(tǒng)的市場(chǎng)競爭力。除了這些問題，還有一個(gè)建議的方法就是將FPLDs在硬件樣機(jī)中最為中介手段，，然而這種方法將會(huì)給樣機(jī)的設(shè)計(jì)帶來額外的工作。而且樣機(jī)上的模塊不能被直接重復(fù)利用。在市場(chǎng)上，有一些公司提供基于FPLDs的速成樣機(jī)的商業(yè)解決方案。這些產(chǎn)品旨在對(duì)片上系統(tǒng)的功能檢查，而不是以嵌入式系統(tǒng)的設(shè)計(jì)和發(fā)展為目標(biāo)。
在這篇論文里，我們將提供自行設(shè)計(jì)的基于ARM的嵌入式系統(tǒng)的速成樣機(jī)平臺(tái)，這是一種低成本的解決方案，并且符合在嵌入式系統(tǒng)樣機(jī)發(fā)展方面對(duì)于靈活性和可測(cè)試性的要求。它同樣支持系統(tǒng)硬件各個(gè)部分的更新和模塊的再利用。
論文剩下部分的結(jié)構(gòu)是這樣的：第二部分，我們將討論自行設(shè)計(jì)的速成樣機(jī)平臺(tái)的細(xì)節(jié)。第三部分，將展示實(shí)驗(yàn)的結(jié)果，接下來的第四部分是全面的結(jié)論。
2.速成樣機(jī)平臺(tái)設(shè)計(jì)
A 總攬
基于ARM的嵌入式處理器被廣泛應(yīng)用于嵌入式系統(tǒng)，這是由于它們的低成本，低功耗和高性能?；贏RM的嵌入式處理器是高度集成的片上系統(tǒng)，它包括一個(gè)ARM內(nèi)核，和各種各樣地外圍設(shè)備。很多基于ARM的嵌入式處理器，比如：[6]~[8]采用一種簡單的結(jié)構(gòu)就像Fig.1 所示。
集成存儲(chǔ)器控制器提供外部存儲(chǔ)器總線接口，這種接口支持各種各樣的存儲(chǔ)器芯片和各種操作模式（同步，異步，突發(fā)模式）。而且可以將擴(kuò)展總線的外圍芯片連接到存儲(chǔ)器總線上。片上外圍設(shè)備應(yīng)該包括中斷控制器，操作系統(tǒng)時(shí)鐘，UART（通用異步收發(fā)器），I2C（兩線式串行總線），PWM（脈寬調(diào)制），AC97（一種聲卡）等等。其中一些外圍設(shè)備的信號(hào)是多元的，它們都有多功能的數(shù)字I/O管腳來為用戶提供方便，而其它的一些片上外圍設(shè)備，例如：USB主機(jī)/客戶機(jī)，就會(huì)提供專用的外圍設(shè)備信號(hào)管腳。通過連接或是擴(kuò)展這些管腳，用戶可以利用這些片上外圍設(shè)備。當(dāng)片上外圍設(shè)備不能滿足目標(biāo)系統(tǒng)的要求時(shí)，就得擴(kuò)展額外的外圍設(shè)備芯片。
基于ARM的嵌入式系統(tǒng)結(jié)構(gòu)如圖2所示。整個(gè)系統(tǒng)由嵌入式處理器，存儲(chǔ)器設(shè)備，外圍設(shè)備組成。為了設(shè)計(jì)成速成樣機(jī)，那么平臺(tái)應(yīng)該可由各個(gè)模塊通過靈活的方式迅速組裝成一個(gè)整體。我們的基本方法是插入一個(gè)可重新配置的互相連接的模塊，，然后用FPLD組成系統(tǒng)，并且使信號(hào)間的連接可調(diào)整，同時(shí)使其具有可測(cè)試性。在決定如何設(shè)置這樣的模塊之前，我們首先應(yīng)該分析系統(tǒng)的結(jié)構(gòu)。
在圖Fig.2中展示的嵌入式系統(tǒng)可以被分為兩部分。一部分是由嵌入式處理器和存儲(chǔ)器設(shè)備構(gòu)成的小型系統(tǒng)。另一部分是由嵌入式處理器的片上外圍接口擴(kuò)展的外圍設(shè)備和有總線擴(kuò)展的外圍芯片、電路組成。
最小限度的系統(tǒng)是嵌入式系統(tǒng)的核心，它決定了嵌入式系統(tǒng)的處理能力。嵌入式處理器的時(shí)鐘頻率可以達(dá)到400MHz，而且可以達(dá)到更高?？偩€連接處
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