【機(jī)械類畢業(yè)論文中英文對(duì)照文獻(xiàn)翻譯】智能交通燈簡述

【機(jī)械類畢業(yè)論文中英文對(duì)照文獻(xiàn)翻譯】智能交通燈簡述,機(jī)械類畢業(yè)論文中英文對(duì)照文獻(xiàn)翻譯,機(jī)械類,畢業(yè)論文,中英文,對(duì)照,對(duì)比,比照,文獻(xiàn),翻譯,智能,交通燈,簡述 Intelligent traffic light With economic development, increased the number of vehicles, road congestion is becoming increasingly serious, intelligent traffic lights on the emerged. At present, the world's Intelligent Transportation System will be: a huge structure, management difficulties, such as the maintenance of large inputs. In order to improve the existing traffic conditions, and to overcome the existing shortcomings of intelligent transportation system I designed analog control traffic lights in urban and rural areas of small-scale smart traffic lights. It has small size, intelligence, maintenance into small, easy to install and so on. And other intelligent transportation system compared to the system to adapt to economic and social development, in line with the current status of scientific and technological development. Intelligent traffic lights are a comprehensive use of computer network communication technology, sensor technology to manage the automatic control system of traffic lights. Urban traffic control system is used for urban traffic data monitoring, traffic signal control and traffic management computer system; it is the modern urban traffic control system command and the most important component. In short, how to use the appropriate control method to maximize the use of costly cities to build high-speed roads, trunk road and the ramp to alleviate urban areas with the neighboring state of traffic congestion has become more and more traffic management and urban planning departments need to address the main problem. To this end, this article on the urban traffic light control system analog circuit theory, design calculation and experimental testing and other issues to discuss specific analysis. The General Situation of AT89C51 Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51. 1.1 Introduction The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components are extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device. 1.2 The AT89C51 provides the following standard features: 4Kbytes of flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. 1.3Pin Description GND Ground. Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses . In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special feature soft the AT89C51 as listed below: RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN：Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin all receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. Chip erase The power to erase the entire Flash array, through the appropriate combination of control signals and by holding ALE / 10 ms compiled low. "1" written in code array chip erase operation must be performed before the code memory can be reprogrammed. Byte of each code in the flash memory array can be written, and the entire array can be erased through the appropriate combination of control signals. Write cycle is self-timed, and once started, will be automatically done. Information between the computer interface into a computer electronic system to process the information outside the two forms. There is a physical signal, it represents the value of the plan. Any interface functions can be divided into the number of operations that modify data in some way, the conversion process between the internal and external form of a number of steps. Analog – digital converter for continuously variable signals into digital form, may be taken by a fixed binary value. If the discontinuous change in the output of the sensor, there is no ADC is necessary. In this case, the signal conditioning section must input signals into a direct connection to the part of the form next to the interface, input / output section of the output interface of the computer itself, takes a similar form, the obvious difference is that the information the flow in the opposite direction, it is through to the outside world, in this case, the program may call an output routine supervision and operator interface, and implementation ratio can be used for digital - analog converter digital . This subroutine in turn pass the information generated, it can be converted into a corresponding electrical signal output device using the DAC analog form. In the form of operating conditions of the last signal for the implementing agency. Almost always used in the microcomputer circuit signal is too small to connect directly to the outside world, you must use some kind of interface translation . they are a more appropriate form of interface circuit part of the design we have seen computer engineers who wish to apply for one of the most important task facing the form of this figure is only the most useful computer connected to the device can be turned on or off, in a discrete bit mode of the micro-computer, where each bit represents a switch or regulator in order to resolve the status of real-world problems, the microcontroller must be more than just a CPU, a program and data memory. in addition, it must include the hardware to allow the CPU to access information from the outside world. Once the CPU to gather information and processing data must be able to change on the outside of some parts of these hardware devices, peripherals, CPU outside the window. The peripheral micro-controller provides the most basic form is a general-purpose I70ports, each I /O pins can be used as input or output. The function of each pin is set or clear the corresponding bit data direction register in the appropriate decisions in the initialization phase of the program, each output pin to drive the CPU instructions used by the pin can be considered to use the program instructions the CPU (or read). Some type of logic 1 or logic 0. Communication function of the serial unit includes a Microcontroller , CPU and external devices to communicate serial format, instead of using bit parallel format and require less I / O pins, which makes it cheaper, but slower The serial transmission synchronous or asynchronous